NIT :: NanoIC Technology Lab

Patents

US PATENTS

  • 23

    S. H. Park, C. Y. Yoo, H. S. Kim, M. S. Seo, D. K. Kim, B. J. Cho, "HIGH TEMPERATURE STRUCTURE FOR MEASURING OF PROPERTIES OF CURVED THERMOELECTRIC DEVICE, SYSTEM FOR MEASURING OF PROPERTIES OF CURVED THERMOELECTRIC DEVICE USING THE SAME AND METHOD THEREOF", US Patent, 15/217,429, 2016. (Patent pending)

  • 22 B. J. Cho, H. J. Ahn, J. M. Moon, "Semiconductor element, method for fabricating the same, and semiconductor device including the same", US Patent, 9,450,064, 2016.
  • 21 B. J. Cho, S. G. Im, S. J. Yoon, K. Pak, H. A. Yoon, "Method of sealing open pores on surface of porous dielectric material using iCVD process", US Patent, 15/247,817, 2016. (Patent pending)
  • 20 B. J. Cho, S. J. Kim, J. H. We, "Thermoelectric device using substrate and manufacturing method thereof", US Patent, 14/372,037, 2014. (Patent pending)
  • 19 Byung Jin Cho and Jeong Hun Mun, "Board and method for growing high-quality graphene layer", US patent, 14/132121, 2013.
  • 18 Byung Jin Cho and Jeong Hun Mun, "Method and board for growing high-quality graphene layer using high pressure annealing", US patent 20140299975 A1, 2014.
  • 17 B. J. Cho, J. H. Bong, O. Sul, H. A. Yoon, "Method of Manufacturing N-Doped Graphene and Electrical Component Using NH4F, and Graphene and Electrical Component Thereby", US patent, 14/256895, 2014. (Patent pending)
  • 16

    H. J. Song, B. J. Cho, S. A. Seo, W. C. Shin, "Graphene electronic devices having multi-layered gate insulating layer", US patent, No. US 20120313079 A1, 2012. (Patent pending)

  • 15

    B. J. Cho, J. K. Park, "NON-VOLATILE MEMORY DEVICE AND MOSFET USING GRAPHENE GATE ELECTRODE", US patent, No. US 8,638,614 B2, Jan. 28, 2014.

  • 14

    B. J. Cho, J. H. Mun, "Graphene device having physical gap", US patent, No. US 8,637,851 B2, Jan. 28, 2014.

  • 13

    C. S.Park, B.J.Cho, N. Balasubramanian, "Method of fabricating a CMOS device with dual metal gate electrodes". US patent 7,316,950, 2008.

  • 12

    C. H. Poon, B. J. Cho, Y. F. Lu, A. See, M. Bhat, "Method of multiple pulse laser annealing to active ultra-shallow junctions", US patent 6,897,118 B1, 2005.

  • 11

    S. A. Jang, T. S. Song, Y. B. Kim, B. J. Cho, and J. C. Kim, "Method for forming element isolating film of semiconductor device", US patent 6,027,985, 2000.

  • 10

    S. A. Jang, B. J. Cho, and J. C. Kim, "Method for forming field oxide film of semiconductor device", US patent 6,013,561, 2000.

  • 9

    S. A. Jang, T. S. Song, Y. B. Kim, B. J. Cho, and J. C. Kim, "Method for forming element isolating film of semiconductor device", US patent 5,940,719, 1999.

  • 8

    S. A. Jang, Y. B. Kim, M. S. Joo, B. J. Cho, and J. C. Kim, "Method for forming field oxide of semiconductor device using wet and dry oxidation", US patent 5,985,738, 1999.

  • 7

    Y. B. Kim, S. K. Kwon, and B. J. Cho, "Method for isolating elements of semiconductor device", US patent 5,719,086, 1998.

  • 6

    K. H. Lee and B. J. Cho, "Method for removing defects by ioin implantation using medium temperature oxide layer", US patent 5,846,887, 1998.

  • 5

    B. J. Cho, "Method for manufacturing a non-volatile memory cell", US patent 5,610,091, 1997.

  • 4

    B. J. Cho, "Apparatus for manufacturing a semiconductor layer using rapid thermal processing", US patent 5,499,602,1996.

  • 3

    B. J. Cho, "Method for forming a gate electrode in a semiconductor devices", US patent 5,536,667, 1996.

  • 2

    B. J. Cho, "Method for forming an oxynitride film in a semidoncuctor devices", US patent 5,541,141, 1996.

  • 1

    B. J. Cho, "Method of manufacturing a semiconductor devices", US patent 5,559,049, 1996.