High-k / Metal gate using Atomic Layer Deposition
Scaling down of traditional 2D MOSFET is saturated due to physical limitation, therefore transition to 3D structures is essential in semiconductor industry. However, film deposition process used in traditional 2D MOSFET is planar. To fabricate 3D structure in high density IC, conformal film deposition process which can cover high aspect ratio structure or precise, complicated structure such as nanowire is essential. ATOMIC-LAYER DEPOSITION provides one means for coating a semiconductor wafer with a high-k insulator and meta gate. The benefit of this technique is that it offers atomic-scale control of the coating thickness without requiring elaborate equipment. The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic-scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required.
The Germanium is one of the candidates for beyond the Silicon-based MOSFET because of high mobility. However, unlike excellent interfacial qualities in SiO2/Si interface, GeO2 layer has water solubility and thermal instability which make it very difficult to fabricate high-quality Germanium gate stack. The core goals for Ge MOSFET is to maintain the stable gate stack for high quality device performances and at the same time, minimize the EOT.
As the feature-size of modern Cu interconnects has been scaled down, RC delay problem in BEOL has become a main bottleneck of the chip performance. Our group is focusing on the comprehensive solution for the advanced interconnects system to suppress RC delay, including ultralow-k dielectrics (k<2.0) and alternative metals (e.g. Cobalt and Ruthenium).
Investigate Fluorine effect on 3D NAND Flash Memory
CVD and ALD are widely used for gate stack deposition of 3D NAND Flash memory. Specially CVD-W is very effective to deposit the word line in deep and narrow via due to its high vapor pressure. WF6 is main precursor of CVD W and it contains lots of fluorine component. Fluorine is known as high reactive, toxic, and electronegative but the effect of fluorine on NAND Flash cell is still debating. Therefore it is important to investigate the effect of fluorine on reliability and performance of NAND Flash memory device.